module tb_ShiftRows();
  
  wire [31:0] col0_sft_dec;
  wire [31:0] col1_sft_dec;
  wire [31:0] col2_sft_dec;
  wire [31:0] col3_sft_dec;
  
  wire [31:0] col0_sft;
  wire [31:0] col1_sft;
  wire [31:0] col2_sft;
  wire [31:0] col3_sft;
  
  reg [31:0] col0;
  reg [31:0] col1;
  reg [31:0] col2;
  reg [31:0] col3;
  reg enc_dec;
  
  shiftRows SR_ENC
  (
    //OUTPUTS
    .col0_sft(col0_sft),
    .col1_sft(col1_sft),
    .col2_sft(col2_sft),
    .col3_sft(col3_sft),
    
    //INPUTS
    .col0(col0),
    .col1(col1),
    .col2(col2),
    .col3(col3),
    .enc_dec(enc_dec) 
  );
  
    shiftRows SR_DEC
  (
    //OUTPUTS
    .col0_sft(col0_sft_dec),
    .col1_sft(col1_sft_dec),
    .col2_sft(col2_sft_dec),
    .col3_sft(col3_sft_dec),
    
    //INPUTS
    .col0(col0_sft),
    .col1(col1_sft),
    .col2(col2_sft),
    .col3(col3_sft),
    .enc_dec(~enc_dec) 
  );
  
  integer i;
  initial
    begin
      enc_dec = 1;
      //col0 = 32'h03_02_01_00;
      //col1 = 32'h07_06_05_04;
      //col2 = 32'h0B_0A_09_08;
      //col3 = 32'h0F_0E_0D_0C;
      col0 = 32'hbe_e3_3d_19;
      col1 = 32'h2b_e2_f4_a0;
      col2 = 32'h2a_8d_c6_9a;
      col3 = 32'h08_48_f8_e9;
    end
endmodule
